This invention relates to an analog belief propagation, and in particular to a current mode implementation of belief propagation a processor.
Soft logic processing with analog values has a number of applications, including in decoding of Low Density Parity Check (LDPC) codes. A number of algorithms have been proposed for processing digital or analog representations of values, including the Sum-Product (SP) algorithm, which is sometimes referred to as a Belief Propagation Algorithm, and the Min-Sum (MS) algorithm (also referred to as Max-Sum or Max-Product), which can be regarded as an approximation of the SP algorithm. A description of such algorithms may be found in H. Wymeersch, Iterative Receiver Design, Cambridge University Press, Cambridge, 2007.
One representation of belief propagation process makes use of a bipartite graph referred to as a “factor graph,” which includes variable (equals) nodes and factor (or constraint) nodes. Messages are iteratively passed between the nodes in a convergent process. One specific belief propagation process is used for error correction decoding in which the variables are bits of a codeword, and the factors are parity constraints among subsets of bits of the codeword.
Circuit implementations of the min-sum algorithm for error correction decoding generally involve two kinds of soft-gates: equals and XOR, corresponding to variable nodes and factor nodes of a factor graph, respectively. The connectivity of the factor graph that defines the connectively between the soft equals and soft XOR is based on the check-matrix associated with the specific error correcting code. When using a log-likelihood ratio (LLR) representation for the messages, the operations required by the min-sum algorithm for each soft-gate type are as follows.                Soft equals: each output is the sum of all included inputs. For a given output, all inputs are included except the input corresponding to the same edge as the output being computed.        Soft XOR: each input is represented as a sign and magnitude, the latter being the absolute value of the input. The sign of each output corresponds to the product of the sign of all included inputs, treating the sign as +/−1. This is equivalent to the logical XOR of the sign of all included inputs, treating a positive sign as a 0 and minus sign as a 1. The magnitude of each output corresponds to the minimum of the magnitudes of each included input. For a given output, all inputs are included except the input corresponding to the same edge as the output being computed. (For all outputs that do not correspond to the input with the minimum magnitude, the magnitude of the outputs are identical—the value of the minimum input magnitude. For the output corresponding to that input, the output is the minimum of all other inputs.)        